Foundation Course & PD Learning and Reference Materials
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Course Overview
Schedule of Classes
Course Curriculum
5 Subjects
Foundation Course & PD Learning and Reference Materials
66 Learning Materials
Foundation Courses Slides
Digital Design Slides
PDF
CMOS Devices and Technology Slides
PDF
Verilog HDL Slides
PDF
Linux Essentials Basics and GVIM
PDF
Physical Design Slides
Module 1 CMOS and ASIC Design
PDF
Module 2 Synthesis
PDF
Module 3 Data Preparation
PDF
Module 4 Sanity Checks
PDF
Module 5 PD Flow and Terminology
PDF
Module 6 Floor plan
PDF
Module 7 Power Planning
PDF
Module 8 STA 1
PDF
Module 9 Placement
PDF
Module 10 CTS
PDF
Physical Design - Lab Manuals
Lab Manual 1 - Synthesis logical
PDF
Lab Manual 2 - Synthesis physical
PDF
Lab Manual 3 - Data preparation
PDF
Lab Manual 4 - Floorplan
PDF
Lab Manual 5 - Powerplan
PDF
Lab Manual 6 - Placement
PDF
Lab Manual 7 - CTS
PDF
Lab Manual 8 - Routing
PDF
Lab Manual 9 - Parasitic Extraction
PDF
Lab Manual 10 - Signoff STA
PDF
Lab Manual 11 - ECO Flow
PDF
Lab Manual 12 - Physical Verification
PDF
Synopsys Tool Manuals
IC validator user guide
PDF
ICC Command Reference
PDF
ICC invocation commands
PDF
ICC Technology - Routing Rules Manual
PDF
ICC user guide
PDF
Library preparation guide for ICC
PDF
PT user guide
PDF
SDC Constraints Appnote
PDF
StarRC User Guide
PDF
Timing Constraints _ optimization User guide
PDF
ICC Articles
ADR_AppNotes_201012_v1-2
PDF
Clock-Gating Methodology
PDF
cts_checklist_v2
PDF
CTS_recommendations_and_debugging
PDF
Determining the Exact Net Length
PDF
eco_flow_app_note
PDF
Examples Describing Interclock Delay Balancing Usage
PDF
Fixing Hold Time Violations by Inserting Delay at the Data Path Endpoint
PDF
How Are Clock Gating Checks Inferred
PDF
How to Control the Cell Name Prefix of New Cells
PDF
IC Compiler Flow With Crosstalk Pevention and Fixing
PDF
Identifying Buffers Added During Hold Fixing
PDF
ICC_CTS_sweet_spot_v12_custom
PDF
Incremental Congestion Removal After Clock Tree Synthesis
PDF
Interclock Delay Balancing During Clock Tree Synthesis
PDF
Interclock Delay Balancing Usage
PDF
J-2014 09_CTS_update_training_slides_General_CTS
PDF
J-2014 09 PG_Tie off_Editing AN
PDF
Physical_IP_Workshop_ARM_CPU_Hardening
PDF
Postroute Clock Tree Optimization
PDF
PrimeTime SI_s Crosstalk Analysis
PDF
Reducing Congestion With IC Compiler
PDF
Removing Shorts Over Macros
PDF
Restricting Clock Tree Cells
PDF
SDC and CTS
PDF
Viewing and Reporting Errors Found by the verify_pg_nets Command
PDF
What Are the Issues Involving Recalculating Reconverging Clock Paths
PDF
Reference Books
Digital Circuit
PDF
ICC2ug
PDF
Static-Timing-Analysis-for-Nanometer-Designs
PDF
Digital Design
46 Learning Materials
Digital Fundamentals
Introduction - 1
Video
2:59
Analog and Digital Signal
Video
4:48
How Digital Signals Obtained
Video
7:28
Digital System Over Analog System
Video
4:7
Summary
Video
040
Number System
Introduction - 2
Video
14:41
Number Based Converstion
Video
35:52
Signed and Unsigned Numbers
Video
24:14
Binary Arithmetic
Video
30:56
Binary Codes
Introduction - 3
Video
3:44
Binary Coded Decimal
Video
4:58
Excess-3 Code and Gray code
Video
7:37
Binary To Gray Code Conversion
Video
9:22
Gray Code To Binary Conversion
Video
6:21
Alphanumeric Codes
Video
2:17
Error Detecting Codes
Video
6:43
Self Complementry Property
Video
9:5
Boolean Algebra
Introduction - 4
Video
4:2
Logic gates
Video
5:56
Boolean Theorems and Properties
Video
11:58
Canonical Standard Forms
Video
9:3
Standard Form to Logic Diagram
Video
3:34
Gate Level Minimisation
Introduction - 5
Video
2:46
Map Methods
Video
8:34
K-MAP Rules
Video
4:8
AOI Implementation
Video
1:56
K Map Examples
Video
23:34
Combinational Logic Circuits
Introduction - 6
Video
5:44
Adders
Video
19:33
Ripple Carry Adder
Video
10:55
Carry Look Ahead Adder
Video
9:53
Decoder
Video
10:20
Encoder
Video
8:44
Multiplexer
Video
11:50
De Multiplexer
Video
7:23
Magnitude Comparator
Video
7:43
Sequential Circuits
Introduction -7
Video
7:13
Flip-Flop
Video
9:57
Latches
Video
9:00
Register
Video
13:29
Counter
Video
13:51
Finite State Machine
Melay and Moore FSM
Video
22:49
Memory
Introduction 7
Video
9:25
RAM
Video
16:16
ROM
Video
11:22
Programmable Logic Devices
PLD,PLA and FPGA
Video
15:14
CMOS Devices and Technology
17 Learning Materials
Electronic Devices and Power Supply
Electronic Components and Power Sources
Video
40:42
Network Theorems
Video
21:46
Semiconductor Physics
Semiconductor Physics basics
Video
41:34
Semiconductor Physics PN Device
Video
24:23
Transistors
BJT and VI Characteristics
Video
35:17
MOSFET and VI Characteristics
Video
31:36
Logic Gate CMOS Implementation
Inveter with different loads
Video
16:58
CMOS logic Gates
Video
18:48
CMOS Boolean Expression Implementation
Video
15:6
Stick Diagram and Layout
Stick Diagram
Video
31:6
CMOS logic gates Layout
Video
18:48
Process Technology
Wafer Manufacturing Process Diffusion Ion Implantation
Video
14:49
NMOS Fabrication Process
Video
1:13:18
Second Order Effects
Body Effect and Channel Length Modulation
Video
28:24
Cross Talk Analysis Delta Delay Antenna Effects
Video
21:59
Punch Through Latch Up DIBL
Video
30:55
Net Parasitics
Interconnect Parasitic ,Parasitic Variations, PVT Conditions
Video
46:14
Verilog for Design & Verification
5 Learning Materials
Language Introduction
Module Module Instantiation Procedural Statement and Test Bench
Video
49:23
Data Types and Operators
Lexical Elements Registers Nets and Operators2
Video
40:50
Sequential Circuit Modeling
Arrays System Tasks and Functions Procedural Assignments
Video
42:5
Procedural Timing Controls & amp Conditional Statements
Race Conditions Timing Control Block Statements Conditional and Loop Statements
Video
45:46
Tasks and Functions
Tasks Functions Q and A
Video
39:43
Essentials Of LINUX
6 Learning Materials
LINUX Commands
Introduction
Video
11:13
Text Processing Commands
Video
50:38
Process Management and Archival Commands
Video
23:12
File Permission Commands
Video
17:8
GVIM
Introduction
Video
9:47
Modes of Operation
Video
38:38
Course Instructor
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